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PI74SSTVF16859
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
13-Bit to 26-Bit Registered Buffer
Product Features
* PI74 SSTVF16859 is designed for low-voltage operation, 2.5V for PC1600 ~ PC2700; 2.6V for PC3200 * Supports SSTL_2 Class I specifications on outputs * All Inputs are SSTL_2 Compatible, except RESET which is LVCMOS. * Designed for DDR Memory * Flow-Through Architecture * Packages: 64-pin, 240-mil wide plastic TSSOP (A) 56-pin, Plastic Very Thin Fine Pitch Quad Flat No Lead QFN (ZB)
Product Description
Pericom Semiconductor's PI74SSTVF16859 logic circuit is produced using the Company's advanced sub-micron CMOS technology, achieving industry leading speed. All inputs are compatible with the JEDEC standard for SSTL_2, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compatible. The device operates from a differential clock (CLK and CLK). Data registered at the crossing of CLK going HIGH, and CLK going LOW. The PI74SSTVF16859 supports low-power standby operation. When RESET is LOW, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RESET is LOW, all registers are reset, and all outputs are forced LOW. The LVCMOS RESET input must always be held at a valid logic HIGH or LOW level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the LOW state during power up. In the DDR DIMM application, RESET is specified to be completely asynchronous with respect to CLK and CLK. Therefore, no timing relationship can be guaranteed between the two. When entering RESET, the register will be cleared and the outputs will be driven LOW quickly, relative to the time to disable the differential input receivers, thus ensuring no glitches on the output. However, when coming out of RESET, the register will become active quickly, relative to the time to enable the differential input receivers. When the data inputs are LOW, and the clock is stable, during the time from the LOW-to-HIGH transition of RESET until the input receivers are fully enabled, the design must ensure that the outputs will remain LOW. Pericom's PI74SSTVF16859 is characterized for operation from 0C to 70C.
Logic Block Diagram - TSSOP
CLK CLK RESET D1 VREF 48 49 51 35 45
16 R CLK
V
Q1A Q1B
D
32
TO 12 OTHER CHANNELS
Logic Block Diagram - QFN
CLK CLK RESET D1 VREF 35 36 38 24 32
7 R CLK
V
Q1A Q1B
D
22
TO 12 OTHER CHANNELS
Product Pin Description
Pin Name RESET CLK CLK D Q GND VDD VDDQ VREF De s cription Reset (Active Low) LVCMOS Clock Input, Positive Differential Input Clock Input, Negative Differential Input Data Input, D1- D13 Data Output, Q1- Q13 Ground Core Supply Voltage Output Supply Voltage Input Reference Voltage
1
Truth Table(1)
Inputs RESET L H H
Notes: 1. H L X
Outputs CLK D X or Floating H L X Q L H L Q o( 2 )
CLK X or Floating L or H
X or Floating L or H
= High Signal Level 2. Output level before the = Low Signal Level indicated steady state = Transition LOW-to-HIGH input conditions were = Transition HIGH-to-LOW established. = Irrelevant or floating
PS8657 02/13/03
VDDQ
VDDQ
Q8A
Q9A
VDD
D13
D12
Q12A Q11A Q10A Q9A VDDQ GND Q8A Q7A Q6A Q5A Q4A Q3A Q2A GND Q1A Q13B VDDQ Q12B Q11B Q10B Q9B Q8B Q7B Q6B GND VDDQ Q5B Q4B Q3B Q2B Q1B
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
63 62 61 60 59 58 57 56 55 54
GND D13 D12 VDD VDDQ GND D11 D10 D9 GND D8 D7 RESET GND CLK CLK VDDQ VDD VREF D6 GND D5 D4 D3 GND VDDQ VDD D2 D1 GND VDDQ
Q7A Q6A Q5A Q4A Q3A Q2A Q1A Q13B VDDQ Q12B Q11B Q10B Q9B Q8B 1 2 3 4 5 6 7 8 9
56 55 54 53 52 51 50 49 48 47 46 45 44 43
D11
Q13A
1
64
VDDQ
VDDQ
Q10A
Q11A
Q12A
Q13A
GND
VDDQ
VDDQ
VDDQ
VDD
D1
D2
Q7B
Q6B
Q5B
Q4B
Q3B
Q2B
45 44 43 42 41 40 39 38 37 36 35 34 33
Maximum Ratings (Above which the useful life may be
impaired. For user guidelines, not tested.)
Ite m Storage Temperature Supply Voltage Symbol/ Conditions Tstg VD D or VD D Q VI VO IIK , VI<0 or VI >VD D IO K , VO <0 or VO >VD D Q IO , VO = 0 to VD D Q ID D , ID D Q or IG N D Ratings -65 to 150 -0.5 to 3.6 -0.5 to VD D +0.5 -0.5 to VD D Q +0.5 50 50 mA 50 100 V Units C
Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2. This value is limited to 3.6V Maximum. 3. The package thermal impedance is calculated in accordance with JESD 51.
Input Voltage(1 ,2 ) Output Voltage
(1 , 2 )
Input Clamp Current Output Clamp Current Continuous Output Current VD D , VD D Q or GND Current/Pin Package Thermal (3 ) impedance A Package 2 B- Package
Q1B
O JA
55 C/W 24
2
PS8657
D3
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74SSTVF16859 13-Bit to 26-Bit Registered Buffer
Product Pin Configurations
42 41 40 39 38
D10 D9 D8 D7 RESET GND CLK CLK VDDQ VDD VREF D6 D5 D4
56-Pin ZB
37 36 35 34 33 32 31 30
64-Pin A
53 52 51 50 49 48 47 46
10 11 12 13
14 29 15 16 17 18 19 20 21 22 23 24 25 26 27 28
02/13/03
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74SSTVF16859 13-Bit to 26-Bit Registered Buffer
Recommended Operating Conditions(4)
Parame te rs De s cription Core Output Supply Voltage VDD/VDDQ I/O Supply Voltage PC1600 P C 2700 P C 3200 PC1600 P C 2700 P C 3200 VTT VI VIH VIL VIH VIL VIH VIL VICR VID IOH IOL TA Termination Voltage Input Voltage AC High - Level Input Voltage AC Low - Level Input Voltage Data Inputs DC High - Level Input Voltage DC Low - Level Input Voltage High - Level Input Voltage RESET Low - Level Input Voltage Common- mode input range CLK, CLK Differential Input Voltage High- Level Output Current Low- Level Output Current Operating Free- Air Temperature 0 0.36 -16 mA 16 70 C 0.97 0.7 1.53 1.7 VREF +150mV VREF -150mV M in. 2.3 2.5 1.15 1.25 VREF -0.04 0 VREF +310mV VREF - 310mV Nom. 2.5 2.6 1.25 1.3 VREF M ax. 2.7 2.7 1.35 1.35 VREF +0.04 VDD V Units
VREF
Reference Voltage VREF = 0.5X VDDQ
Note: 4. The RESET input of the device must be held at VDD or GND to ensure proper device operation. The differential inputs must not be floating, unless RESET is LOW.
3
PS8657
02/13/03
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74SSTVF16859 13-Bit to 26-Bit Registered Buffer
DC Electrical Characteristics for PC1600 ~ PC2700
(Over the Operating Range, TA = 0C to +70C, VDD = 2.5V 200mV, VDDQ = 2.5V 200mV)
Pa ra me te rs VIK VO H Te s t Co nditio ns II = -18 mA IO H = -10 0 A IO H = -8 mA IO L =10 0 A IO H =8 mA VI = VDD o r GN D RES ET = GN D RES ET = VDD VI = VIH(AC ) o r VIL(AC ) RES ET = VDD VI = VIH(AC ) o r VIL(AC ) C LK and C LK switching 5 0 % d uty cycle RES ET = VDD VI = VIH(AC ) o r VIL(AC ) C LK and C LK switching 5 0 % d uty cycle. O ne d ata inp ut switching at half clo ck freq uency, 5 0 % d uty cycle VI = VREF 3 10 mV VIC R = 1. 2 5 V, VI(PP) = 3 6 0 mV VI = VDD o r GN D 2.5V 2.5 2.5 30 IO = 0 2.7V VD D 2.3V 2 . 3 V- 2 . 7 V 2.3V 2 . 3 V- 2 . 7 V 2.3V 2.7V VDD - 0 . 2 1.95 0.2 0.35 5 10 25 A mA A/ clo ck MHz A/ clo ck MHz d a ta inp ut 3.5 3.5 V M in. Typ. M ax. - 1.2 Units
VO L II IDD All Inp uts S tand b y (S tatic) O p erating (S tatic)
Dynamic O p erating clo ck o nly IDDD Dynamic O p erating p er each d ata inp ut
10
Data Inp uts CI C LK and C LK RES ET
pF
4
PS8657
02/13/03
DC Electrical Characteristics for PC3200
(Over the Operating Range, TA = 0C to +70C, VDD = 2.6V 100mV, VDDQ = 2.6V 100mV)
Pa ra me te rs VIK VO H Te s t Co nditio ns II = - 1 8 mA IO H = - 1 0 0 A IO H = - 8 mA IO L =1 0 0 A IO H =8 mA VI = VDD o r GN D RES ET = GN D RES ET = VDD VI = VIH(AC ) o r VIL(AC ) RES ET = VDD VI = VIH(AC ) o r VIL(AC ) C LK and C LK switching 5 0 % d uty cycle RES ET = VDD VI = VIH(AC ) o r VIL(AC ) C LK and C LK switching 5 0 % d uty cycle. O ne d ata inp ut switching at half clo ck freq uency, 5 0 % d uty cycle VI = VREF 3 1 0 mV VIC R = 1 . 2 5 V, VI(PP) = 3 6 0 mV VI = VDD o r GN D 2.6V 2.5 2.5 30 IO = 0 2.7V VD D 2.5V 2 . 5 V- 2 . 7 V 2.5V 2 . 5 V- 2 . 7 V 2.5V 2.7V VDD - 0 . 2 1.95 0.2 0.35 5 10 25 A mA A/ clo ck MHz A/ clo ck MHz d a ta inp ut 3.5 3.5 V M in. Ty p. M ax. - 1.2 Units
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74SSTVF16859 13-Bit to 26-Bit Registered Buffer
VO L II IDD All Inp uts S tand b y (S tatic) O p erating (S tatic)
Dynamic O p erating clo ck o nly IDDD Dynamic O p erating p er each d ata inp ut
10
Data Inp uts CI C LK and C LK RES ET
pF
5
PS8657
02/13/03
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74SSTVF16859 13-Bit to 26-Bit Registered Buffer
Timing Requirements (over recommended operating free-air temperature range, unless otherwise noted)
VDD =2 .5 V 0 . 2 V M in. fclo ck tW ta c t C lo ck F req uency P ulse Duratio n, C LK , C LK High o r Lo w Differential inp uts active time, d ata inp uts must b e lo w after RES ET High Differential Inp uts inactive time, d ata and clo ck inp uts must b e held at valid levels (no t flo ating) after RES ET Lo w Data b efo re C K , C K 2.5 22 M ax. 270 2.5 22 VDD =2 .6 V 0 . 1 V M in. M ax. 270 Units MHz
tinact
22 ns 0.75 0.9 0.75 0.9 0.75 0.9 0.75 0.9
tS U
S etup time, slo w slew rate Ho ld time, fast slew rate
(6 , 7 )
(5 , 7 ) (6 , 7 )
th
Ho ld time, slo w slew rate
Data b efo re C K , C K
Notes: 5. Data signal input slew rate 1 V/ns 6. Data signal input slew rate 0.5V/ns and <1V/ns 7. CLK, CLK input slew rates are 1 V/ns.
Switching Characteristics for PC1600 ~ PC2700
(over recommended operating free-air temperature range, unless otherwise noted.) (See test circuits and switching waveforms).
Parame te r fmax tpd tphl CLK, CLK RESET Q Q From (Input) To (Output) VDD = 2.5V 0.2V M in. 210 1.1 2.2 5.0 Typ. M ax. Units MHz ns
Switching Characteristics for PC3200
(over recommended operating free-air temperature range, unless otherwise noted.) (See test circuits and switching waveforms).
Parame te r fmax tpd tphl CLK, CLK RESET Q Q From (Input) To (Output) VDD = 2.6V 0.1V M in. 210 1.1 2.2 5.0 Typ. M ax. Units MHz ns
6
S etup time, fast slew rate
(5 , 7 )
PS8657
02/13/03
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74SSTVF16859 13-Bit to 26-Bit Registered Buffer
Test Circuit and Switching Waveforms
LVCMOS RESET Input
VDD/2
VDD 0V
From Output Under Test 500 Test Point CL = 30pF(8)
t inact
IDD(9) 10%
tact
90% IDDH IDDL
Load Circuit
Voltage and Current Waveforms Input Active and Inactive Times
Timing Input VICR t PLH Output
VIL
VICR t PHL VTT
VI(PP)
tw
VIH Input VREF VREF
VOH VOL
VTT
Voltage Waveforms - Pulse Duration
Voltage Waveforms - Propagation Delay Times
Timing Input tsu Input
VREF
VICR
VI(PP)
LVCMOS RESET Input
VDD/2 t PHL
VIH VIL VOH VTT VOL
th
VIH VREF VIL
Output
Voltage Waveforms - Setup and Hold Times
Voltage Waveforms - Propagation Delay Times
Parameter Measurement Information Notes: 8. CL includes probe and jig capacitance. 9. IDD tested with clock and data inputs held at VDD or GND, and IO = 0mA. 10. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 ohms. Input slew rate = 1V/ns 20% (unless otherwise specified). 11. The outputs are measured one at a time with one transition per measurement. 12. VTT = VREF = VDDQ/2 13. VIH = VREF + 310mV (ac voltage levels) for SSTL inputs. VIH = VDD for LVCMOS input. 14. VIL = VREF -310mV (ac voltage levels) for SSTL inputs. VIL = GND for LVCMOS input. 15. tPLH and tPHL are the same as tpd.
7
PS8657
02/13/03
0.25 C A
X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS Notes: 1. Controlling dimensions in millimeters 2. Ref: JEDEC MO-220 variation VLLD-2
Ordering Information
Orde ring Code PI74SSTVF16859A PI74SSTVF16859ZB Package Type 64- Pin TSSOP 56- Pin QFN Te mpe rature Range 0C to 70C
Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com
8
PS8657 02/13/03
0.08 C
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74SSTVF16859 13-Bit to 26-Bit Registered Buffer
64-Pin TSSOP (A) Package
64
.236 .244
6.0 6.2
1
.665 .673
16.9 17.1 1.20 .047 Max. SEATING PLANE
0.45 .018 0.75 .030 .319 BSC 8.1
.004 .008 0.09 0.20
.004 0.10
.0197 BSC 0.50 .007 0.17 .011 0.27 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS .002 .006 0.05 0.15
56-Pin QFN (ZB) Package
.033 MAX 0.84 .007 .012 0.18 0.30 .008 REF 0.20 0 .0015 0.00 0.04
.311 .319 7.90 8.10
.012 .019 0.30 0.50
.019 BSE 0.50
O 0.10 M C A B
R 0.25 x 3
.311 .319 7.90 8.10
.199 .211 5.05 5.35
0.25 Chamfer
0.25 C B .171 .183 4.35 4.65

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